? 2005 california micro devices corp. all rights reserved. 02/28/05 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 1 CMCPCI102B compactpci ? backplane interface features ? compactpci ? standards compliant ? allows compactpci system cards to be used in any slot ? provides termination fo r up to ten channels ? provides a series switch in each channel ? supports hot-swap capability ? very low capacitance load on each line ? industrial temperature range ? 28-pin tssop package ? lead-free version available applications ? redundant system compactpci ? cards ? hot-swap compactpci cards ? industrial pcs ? telecom/datacom equipment ? instrumentation ? computer telephony ? real-time machine control product description the CMCPCI102Bt/br is a 10-channel backplane interface/termination ic sp ecifically designed for com- pactpci redundant system-slot cards. the CMCPCI102Bt/br allows compactpci boards to interface to the backplane and prov ides the versatility to use system cards in any slot (system or peripheral). per the compactpci specif ication, the CMCPCI102Bt/ br provides a 10 ? termination resistor for each chan- nel to terminate the transmission line stub on the board. an integral series switch and associated control signal (sw_en) permits connection/disconnection of the channel, so that the device side of the circuit may be isolated from the backplane side. the compactpci standard requires system boards to be hot-swappable. to accommodate this requirement, the CMCPCI102Bt/br features a switched 10k ? resis- tor connected to the 1v precharge supply voltage. if the precharge enable pin (p_en) is asserted, then the 10k ? pull-up resistors are connected to precharge the circuits. in addition, a system board requirement mandates either a 1.0k ? pull-up resistor or a 2.7k ? resistor con- nected to vio. compactpci slot cards must work in either 3.3v or 5v systems, hence the need for both 2.7k ? and 1k ? resistors. if the 3_ en pin is logic high, the 2.7k ? resistor is used as the pull-up. if the 5_en pin is logic high, the 1k ? resistor is used. the CMCPCI102Bt/br integrat es all these functions in a low-profile 28-pin tssop package and is available with optional lead-free finishing. simplified electrical schematic *one of 10 parallel channels is shown. 1v 5_en 3_en vio b1-b10* a1-a10* compactpci device side backplane side p_en sw_en for all enable signals: logic 0 = switch open logic 1 = switch closed r s 10 ? r pu1 10k ? sw pu1 sw pu2 sw pu3 r pu2 2.7k ? r pu3 1k ? sw s
? 2005 california micro devices corp. all rights reserved. 2 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 02/28/05 CMCPCI102B pin descriptions pin(s) name description 1-5 a1 - a5 the backplane-side input signals for channels 1 through 5, respectively. 10-14 a6 - a10 the backplane-side input signals for channels 6 through 10, respectively. 24-28 b1 - b5 the device-side connection for channels 1 through 5, respectively. 15-19 b6 - b10 the device-side connection for channels 6 through 10, respectively. 6 1v a precharge supply voltage input for all channels. this voltage can be less than or equal to vio. 7 p_en the precharge enable input which controls the precharge pull-up resistors. when this active high control signal is set to ?1?, the precharge of all channels is enabled. 8 gnd the ground voltage reference for the CMCPCI102Bt/br. 9 cap a capacitor must be placed from this pin to gnd. the recommended value is 0.01 f,16v. 20 sw_en the series switch enable input. when this active high control signal is set to ?1?, the series switch between the channel?s backplane-side terminal and device-side terminal is closed. when this sig- nal is cleared to ?0?, the switch is open. 21 3_en the enable signal for the device-side channel pull-up mechanism when 3.3v is the supply volt- age. when this active high control signal is set to ?1?, the 2.7k ? pull-up resistor which pulls up the channel to the supply rail is engaged. otherwise, this pin should be set to ?0?. 22 5_en the enable signal for the device-side channel pull-up mechanism when 5v is the supply voltage. when this active high control signal is set to ?1?, the 1k ? pull-up resistor which pulls up the channel to the supply rail is engaged. otherwise, this pin should be set to ?0?. 23 vio the positive supply voltage for the cmcpci 102bt/br. either 3.3v or 5v may be used. 28-pin tssop 1 2 3 4 5 6 7 8 20 19 18 17 21 22 9 10 24 23 25 26 11 12 27 28 a5 1v p_en gnd cap a6 a7 a8 a1 a2 a3 a4 b2 b3 b4 b5 vio 5_en 3_en sw_en b6 b7 b8 b1 13 14 16 15 b9 b10 a9 a10 package / pinout diagram note: this drawing is not to scale. top view
? 2005 california micro devices corp. all rights reserved. 02/28/05 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 3 CMCPCI102B ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. specifications note 1: esd is applied to input / output pins with respect to gnd, one at a time; unused pins are left open. note 2: this parameter guaranteed by design. part numbering information pins package standard finish lead-free finish ordering part number 1 part marking ordering part number 1 part marking 28 tssop CMCPCI102Bt cpci102 b CMCPCI102Br cpci102br absolute maximum ratings parameter rating units vio (supply voltage) -0.5 to +6 v pin voltages 1v, p_en, 3_en, 5_en, sw_en a1-a10 b1-b10 -0.5 to (vio+0.5) -0.5 to (vio+0.5) -0.5 to (vio+0.5) v v v esd withstand voltage human body model, mil-std-883d, method 3015 (notes 1, 2) + 2000 v storage temperature range -65 to +150 c operating temperature range (ambient) -40 to +85 c dc power per resistor 62 mw package power rating 1 w standard operat ing conditions parameter rating units vio (supply voltage) 3 to 5.5 v pin voltages p_en, 3_en, 5_en, sw_en, 1v a1-a10 b1-b10 0 to vio 0 to vio 0 to vio v v v ambient operating temperature range -40 to +85 c
? 2005 california micro devices corp. all rights reserved. 4 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 02/28/05 CMCPCI102B specifications (cont?d) note 1: operating characteristics are over standard operating condit ions unless otherwise specified. note 2: this parameter is guaranteed by design; it is not tested 100%. electrical operating characteristics (note 1) symbol parameter conditions min typ max units r s1 series resistance through r s a to b; switch sw s closed; t a =25c 51015 ? r s2 series resistance through r s a to b; switch sw s open; t a =25c 1m ? r pu1 resistance of r pu1 pull-up t a =25c 9.5 18 k ? tol rpu2 tol rpu3 resistance tolerance (r pu2 and r pu3 ) t a =25c + 5% tcr pu temperature coefficient of resistance (r pu1 , r pu2 , r pu3 ) -100 ppm/c c 1 capacitance on backplane side (a side) of series resistor r s measured @ 66mhz, 0vdc, sw_en=0v; note 2 1.9 pf c 2 capacitance on device side (b side) of series resistor r s and series switch sw s measured @ 66mhz, 0vdc, vio=5v, 5_en=5v sw_en=0v; note 2 4.2 pf v il logic low input voltage to p_en, 3_en, 5_en, sw_en -0.5 [vio] x 0.3 v v ih logic high input voltage to p_en, 3_en, 5_en, sw_en [vio] x 0.7 [vio] + 0.5 v i leak leakage current into p_en, 3_en, 5_en, sw_en gnd < v < vio + 1+ 10 a i gnd supply current for internal circuits (measured at gnd pin) 0.25 1 m a t plh switch sw s closure delay from the low-to-high transition of sw_en note 2, ?cap? pin capaci- tor=0.01 f 14 ms t phl switch sw s delay from the high-to- low transition of sw_en note 2, ?cap? pin capaci- tor=0.01 f 12 s t ppu propagation delay for pull-up switches sw pu1 , sw pu2 , and sw pu3 , all transitions note 2 10 ns
? 2005 california micro devices corp. all rights reserved. 02/28/05 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 5 CMCPCI102B performance information resistance variation with input voltage the series resistance r s varies with input voltage and supply voltage, as shown in figure 1 . figure 1. resistance variation vs. input voltage resistance variation with temperature the series resistance r s also varies with temperature, as shown in figure 2 . figure 2. resistance variation vs. temperature cap pin capacitance some external capacitance is necessary to prevent the voltage on the cap pin fr om falling during sustained data transfers through the device. this ensures that the logic 1 level does not degrade. the time required to open and close the series switch, sws, varies according to how much capacitance is present on the cap pin. the minimum usable value is 200pf, placed close to the pins. a 0.01uf, 16v capacitor is recommended. see figure 3 and figure 4 for variation of switch on/off times vs. capacitance. figure 3. switch on time vs. cap capacitor value figure 4. switch off time vs. cap capacitor value variation of 10r resistor with i/o voltage, t=25'c 5 6 7 8 9 10 11 12 13 14 15 0123456 i/o voltage [ v ] resistance [ ? ] vc c 5.5 vc c 3.0 conditions: curve v cc 3v in 0: curve v cc 3v in 3: curve v cc 5v in 0: curve v cc 5v in 5: v io = 3.0v v io = 3.0v v io = 5.5v v io = 5.5v channel voltage = 0.0v channel voltage = 3.0v channel voltage = 0.0v channel voltage = 5.5v temperature variation of 10r resistor 5 6 7 8 9 10 11 12 13 14 15 -40 -20 0 20 40 60 80 100 temperature [ o c] resistance [ ? ] v cc 5v in 0 v cc 5v in 5 v cc 3v in 0 v cc 3v in 3 switch on time vs. cap capacitor value 0 2 4 6 8 10 12 14 16 0 2000 4000 6000 8000 10000 12000 capacitor value on cap pin [pf] sws closing tim e [ms] switch off time vs. cap capacitor value 0 2 4 6 8 10 12 14 0 2000 4000 6000 8000 10000 12000 capacitor value on cap pin [pf] sws opening time [ s]
? 2005 california micro devices corp. all rights reserved. 6 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 02/28/05 CMCPCI102B performance information (cont?d) capacitance variation with frequency the a-side and b-side capacitances, c 1 and c 2 , will vary with frequency. the backplane capacitance, c 1, is very linear over a wide frequency range. figure 5 shows a plot of input line a3 (pin 3), measured with sw_en=0v and vio=5v. figure 5. c 1 (backplane-side) capacitance variation vs. frequency the compactpci device si de of the CMCPCI102Bt/ br has a fairly low capacitance (c 2 ) at 66mhz, but it is higher at lower frequencies. figure 6 shows a plot of output line b3 (pin 26), mea- sured at the worst-case (for capacitance) conditions of sw_en=0v, 5_en=0v, 3_en=0v and vio=5v. the increased capacitance at low frequencies is due to the parasitic capacitance of the switches connected to the pull-up resistors. at high frequencies, this parasitic capacitance is decoupled by the pull-up resistors. figure 6. c 2 (device-side) capacitance variation vs. frequency
? 2005 california micro devices corp. all rights reserved. 02/28/05 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 7 CMCPCI102B application information board layout recommendations the CMCPCI102Bt/br devices should be located on the board as close as possi ble to the compactpci con- nector. whether a signal is terminated or not depends upon application, as shown in the following table: figure 7 shows a 64-bit system board connection between the CMCPCI102Bt/br termination and the compactpci 5-row connector (2 mm pitch) labeled a to e (row f is ground). the system slot should have signal lengths not exceeding 63.5 mm (2.5 inches). to minimize trace length, it is recommended that the CMCPCI102Bt/brs be placed on alternate sides of the pc board. the config uration shown illustrates a fully-terminated 64-bit board utilizing 10 CMCPCI102Bt/br devices. some applications (e.g. 32-bit boards) do not require all lines to be terminated, per the above table. the CMCPCI102Bt/br resistors have a very low tcr ( typically -100ppm/c) so that resistance will not fluctu- ate over temperature. buffers are implemented on p_en, 5_en and 3_en inputs to ensure that switches turn on and off completely. a typical system slot card may use 10 CMCPCI102Bt/ br devices to replace 10 10-bit fet bus switches and 76 4-resistor packs (0805 form factor), thus providing significant reduction in both component count and assembly costs. at the same time this highly integrated solution improves reliabilit y and manufacturing effi- ciency, saves board area for space-critical designs, and satisfies compactpci height requirements. figure 7. schematic for 64-bit system board signal(s) system slot boards 32-bit 64-bit ad0-ad31 terminate terminate c/be0#-c/be3# terminate terminate par terminate terminate frame# terminate terminate irdy# terminate terminate trdy# terminate terminate stop# terminate terminate lock# terminate terminate devsel# terminate terminate perr# terminate terminate serr# terminate terminate rst# terminate terminate req64# terminate terminate ack64# terminate terminate inta#, intb#, intc#, intd# (if used) terminate terminate ad32-ad63 n/a terminate c/be4#-c/be7 n/a terminate par64 n/a terminate * * * * * * placed on bottom side of pc board
? 2005 california micro devices corp. all rights reserved. 8 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 02/28/05 CMCPCI102B mechanical details tssop mechanical specifications CMCPCI102Bt/br devices are supplied in 28-pin tssop packages. dimensions are shown below. for complete information on the tssop-28 package, see the california micro devices tssop package information document. * this is an approximate number which may vary. package dimensi ons for tssop-28 package dimensions package tssop pins 28 dimensions millimeters inches min max min max a ? 1.10 ? 0.0433 a1 0.05 0.15 0.002 0.006 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 d 9.60 9.80 0.378 0.386 e 4.30 4.50 0.169 0.177 e 0.65 bsc 0.0256 bsc h 6.25 6.50 0.246 0.256 l 0.50 0.70 0.020 0.028 # per tube 50 pieces* # per tape and reel 1000 pieces controlling dimension: millimeters mechanical package diagrams e d h top view l end view c e b a a1 seating plane side view 5678 910 1234 24 23 22 21 20 19 28 27 26 25 pin 1 marking 11 12 13 14 18 17 16 15
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